1.Field of the Invention
The present invention relates to a semiconductor memory device, and in particular relates to a synchronous type semiconductor memory device which takes in external signals in synchronization with a clock signal which is externally and periodically fed thereto. More particularly, the invention relates to a random accessible synchronous semiconductor memory device (SDRAM).
2. Description of the Related Art
In recent years, microprocessing units (MPUs) have been improved to achieve a higher operation speed. Meanwhile, an operation speed of dynamic random access memories (will be referred to as "DRAMs" hereinafter), which have been used as a main storage, cannot yet follow the operation speed of the MPUs, although the DRAMs have also been improved to achieve a higher speed. Therefore, an access time and a cycle time of the DRAMs may form bottleneck reducing an overall performance of a system in many cases.
A high-speed memory, i.e., a so-called cache memory formed of a high-speed static random access memory (will be referred to as an "SRAM" hereinafter) has often been used in a position between a DRAM and an MPU in order to improve the performance of the system. Data which will be frequently used is stored in the cache memory, and the high-speed cache memory is accessed if data required by the MPU is stored in the cache memory. The DRAM is accessed only when the cache memory does not contain the data required by the MPU. Since the data to be used frequently is stored in the high-speed cache memory, a frequency of access to the DRAM is significantly reduced, so that the performance of the system cannot be affected by the access time and cycle time of the DRAM and thus can be improved.
Since SRAMs are more expensive than DRAMs, the cache memories are not suitable to relatively inexpensive apparatuses such as personal computers. Therefore, it has been desired to improve the system performance with inexpensive DRAMs.
Mere synchronization of the MPU and DRAM can be achieved by applying a system clock to the DRAM to operate the same in synchronization with the system clock. A configuration for synchronizing the DRAM with the system clock is disclosed in the U.S. Pat. No. 5,083,296 to Hara.
The DRAM disclosed in Hara latches a chip select signal /CS and a write enable signal /WE in synchronization with a clock signal CLK. If the latched chip select signal /CS is active and thus indicates that the DRAM is selected, an internal RAS signal and an internal CAS signal are generated in synchronization with the clock signal. In response to the internal RAS signal and internal CAS signal, address signals are latched, and an internal row address signal and an internal column address signal are produced. Input and output of data are also performed in synchronization with the clock signal CLK.
In Hara, the DRAM performs the clock synchronous operation in order to overcome a problem such as deviation of timing which may be caused during operations based on control signals such as a row address strobe signal RAS and a column address strobe signal CAS.
The DRAM of Hara described above is intended merely to perform the clock synchronous operation of the DRAM. The address signal is latched by the internal RAS signal and internal CAS signal generated in synchronization with the clock signal CLK. If a speed of the clock signal is relatively low, or the address signal has a sufficient margin in setup time and a hold time, a desired internal address signal can be produced in response to the external address signal.
However, if the clock signal CLK has a high speed, or the address signal has an insufficient margin in setup time and hold time, such a situation may be caused that the internal address signal has already changed into an invalid state at the time of generation of the internal RAS signal and CAS signal. Therefore, the DRAM of Hara cannot operate in synchronization with a high-speed clock signal, and thus cannot be utilized as a high-speed main storage for a high-speed MPU.
The DRAM of Hara has an internal configuration similar to that of the conventional standard DRAM, and its distinctive feature is only provision of a latch circuit which operates only for external control signals and a data I/O part in accordance with the clock.
Meanwhile, the U.S. JEDEC (Joint Electron Device Engineering Council) has employed synchronous DRAMs (will be referred to as "SDRAMs" hereinafter) which operate in synchronization with clock signals and function as main storages for high-speed MPUs. The U.S. JEDEC is now conducting operations for standardizing specifications of the SDRAMs. The details of these standard specifications have not yet been published. According to the article in "NIKKEI ELECTRONICS", Feb. 3, 1992, page 85, following configurations were proposed.
(1) Synchronization is achieved with a clock signal having a cycle between 10 and 15 ns (nanoseconds).
(2) In a first random access, data is accessed after four to six clocks from input of a row address signal. Thereafter, the data at the consecutive addresses can be accessed at every clock.
(3) A circuit in a chip is operated in a pipelined manner, and a serial I/O buffer is provided in a data I/O part so as to reduce an access time.
The configuration described above is a mere proposal, and specific matters for practically realizing them have not been disclosed at all.